Forming FETs according to gate last or replacement metal gate (RMG) process flows, whether for planar or three-dimensional schemes, involves forming spacers surrounding dummy gates. The spacers cause alignment variations in process flows, which reduces chip yield. Moreover, in process flows that use stress-inducing layers, spacers offset the stress-inducing layers from the channel regions and reduce the beneficial effects of the stress-inducing layers. Such a reduction can be in the form of reduced mobility that would otherwise be caused by the stress-inducing layers, which prohibits drive current improvements. Spacers also cause an offset or gap between the gates and surrounding source/drain regions.
A need, therefore, exists for methodology for forming gates without spacers and the resulting devices.